PDK Engineer

Overview

We have a fantastic opportunity for a PDK Engineer to join our Technology group in Cambridge! Reporting to the Senior PDK Manager and working as part of our collaborative and dynamic PDK team, this is a varied position which will play a key role by contributing significantly to the design, development, maintain and test of Process Design Kits (PDKs) for our released and upcoming in-house semiconductor technologies.

Our FlexIC Foundry makes flexible integrated circuits available to a wide range of customers, each with their own custom application and market area. Our PDK Team supports this by ensuring accurate translation of process capability into the design environment.

This is a critical role which involves backend verification rule‑deck development/maintenance, model card validation and automation, and close support for both analog and digital design flows.

You will be working closely with the Process Development, Modelling and Design teams to enrich the PDK offering and improve its quality. You will also collaborate with the Layout, Design Enablement, Modelling and CAD/EDA teams to ensure our PDKs are robust, accurate, and production‑ready.

We believe this position will be especially attractive to candidates with a keen interest in automation, strong software and Linux skills, and familiarity with the IC design flow.

The position will be based in Cambridge, with hybrid options available; we are also open to considering candidates who will require Visa sponsorship/relocation assistance.

If you are keen to make a positive impact to our PDK team and to work on innovative, exciting technology during a ramp-up phase, we would love to hear from you!

Key tasks

• Develop new PDK features to support both existing and emerging semiconductor technology platforms to ensure timely design enablement

• Develop and maintain backend PDK collateral, including physical verification and validation infrastructure as required

• Maintain and enhance internal PDK development and verification scripts to improve efficiency, reliability, and scalability of workflows

• Develop, automate, and maintain PDK regression test suites to verify functionality and detect issues early in the development cycle

• Collaborate closely with internal stakeholders (design, modelling, CAD/EDA, manufacturing) to clarify requirements and propose efficient technical solutions

• Providing timely technical support and guidance to internal users to maximise design productivity and tape-out success

Qualifications and training

The successful candidate will ideally be educated to degree/post-graduate degree level in Electrical/Electronic Engineering or a related field (or will possess equivalent experience). Ideally you will be able to demonstrate a strong background in electronic design or semiconductor manufacturing processes.

Skills and experience

• Extensive experience with Unix, especially scripting (shell, python, perl)

• Familiarity with Cadence EDA tools and basic knowledge of Skill

• Solid understanding of how a PDK is used in the design flow and how the different components of a PDK fit together

• Familiarity of version control systems (Git, perforce)

• Understanding of SPICE models & verification flows

• Understanding of physical verification flows (DRC, LVS, PEX etc.)

• Good communication & collaboration skills

• Experience with semiconductor manufacturing process (advantage)

• Experience of defining PDK release infrastructure (advantage)

• Experience of other mainstream EDA tools (advantage)

• PCELL development experience (advantage)

• Familiarity with digital design flow (advantage)

• Knowledge of CMOS or TFT process technologies (advantage)

Candidates who do not meet every requirement but feel their skills are a good fit for the role the role are encouraged to apply.

Pragmatic is committed to equity, equality, diversity, and inclusion; we strive to welcome everyone and create inclusive teams. We celebrate difference and encourage everyone to be themselves at work. Please let us know if you would like any adjustments to our application and interview process.