Staff Verification Engineer Job Description Template
Our company is looking for a Staff Verification Engineer to join our team.
Responsibilities:
- Analysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and debug;
- Reviewing and assessing proposed design changes from a verification complexity point of view;
- Ownership of verification environment from investigation all the way to verification closure;
- Close collaboration with other Arm engineering teams leading to high quality IP that works well in a complete system;
- There will be opportunities for improving our verification methodology and mentoring other members of the team;
- Investigating and scripting new verification flows and optimising existing ones.
Requirements:
- Practical experience of working on microprocessor designs;
- Well-versed in the use of hardware verification languages e.g. SystemVerilog or Specman ‘e’
- Ability to quickly understand and apply complex specification detail;
- Understanding of end-to-end verification processes, from test plan creation through to verification closure;
- Experience of designing and implementing verification environments for complex RTL designs;
- In-depth technical reviewing of others’ work;
- Knowledge of assembly language (preferably ARM), and/or C/C++
- Understanding of the fundamentals of computer architecture, with an emphasis on pipelining, exception handling, memory systems,
- Verification methodologies such as UVM;
- In-depth understanding of memory protection, memory translation, vector processing in CPUs, exception and interrupt handling.